DFTSimuLab

DFTSimuLab

Logic simulators and fault simulators

Product Descriptions and Technical Data

The simulators VDLsim and VDFsim provide cost-effective and high-performance logic and fault simulation. Both event-driven and cycle-based evaluation algorithms are supported as well as an application interface, which enables users to compile behavioral-level module descriptions in C into the simulation kernel. The fault simulator supports a wide range of fault models and simulation algorithms.
These products are the results of more than a decade of academic research in the area of fault modeling, gate/switch-level simulation and equivalence checking and many years of industrial experience in DFT productization. The products work well within existing EDA tool environment on UNIX/Linux based workstations. See product option page for simulator options available for various system platforms.

VDLsim (Logic simulator) summary of standard features.

Accepts most Verilog gate-level constructs and a subset of behavior-level constructs.

Supports a wide variety of design styles including asynchronous and synchronous designs.

Provides a unique Simulator C Programming Application Interface, SCPAI, for users to write behavior-level sequential and combinational specifications in C code that are compiled into the simulation kernel for high-speed behavior-level and mixed-mode simulation. This mechanism provides very high flexibility in modeling strategy for both logic simulation and fault simulation.

Provides a standard library model for state elements, which features positive and negative edge-triggered flip flops with asynchronous or synchronous reset/set control, gated clocks and scan cells.

Embedded memory arrays can be modeled using either the SCPAI mechanism for maximum flexibility in memory type, size and read/write controls or using a standard library model.

Analyzes and reports occurrences of combinational feedback, which may lead to oscillation or race. Resolves situation of feedback during run-time if possible and reports net names involved in race.

Provides a compact format for representing input/output vectors in cycle based or event based simulation. Can run in diagnostics mode or playback mode for automatic checking of expected circuit response.

Supports cyclized stimulus description without clock event for high performance simulation of synchronous circuits and with clock event description for complex clocking schemes or asynchronous circuits.

Provides commands for storing and loading flattened models; dumping internal signals; and printing flattened netlist topologies.

Provides toggle coverage analysis reports and has built-in monitors for contention checking of internal nodes.

Provides an interactive command line mode for simulation debug including fan-in cone tracing, X state tracing and node state reporting.

Accommodates both event-driven (0,1,X,Z) and cycle-based zero delay two-state evaluation modes with gate-level and SCPAI modules mixed.

Provides dependency analysis of next-state functions with input constraints.

Writing behavioral-level descriptions in C using the novel SCPAI mechanism avoids a lot of the complexity and performance overhead of standard PLI applications.

VDFsim (Fault simulator) summary of standard features.

VDFsim is a generic sequential fault simulation engine that can be used to fault grade user-defined functional test patterns or ATPG patterns to ensure that the patterns signed off for production test are of sufficiently high quality or to prove that the current test coverage is insufficient.

Accepts the same Verilog netlist constructs as the logic simulator and performs "good circuit" logic simulation integrated within the fault simulation session.

Provides concurrent fault simulation for high-speed sequential fault simulation of synchronous circuits and serial fault simulation mode for asynchronous circuits and for accurate fault simulation of complex clocking schemes under the unit-delay timing model.

Accepts the compressed vector format used in the logic simulator as stimulus format.

Supports stuck-at fault models and several logic and dominance-based bridging fault models.

Generates detailed fault coverage reports and provides several coverage metrics including fault coverage, testable coverage and stimulus efficiency. Categorizes undetectable faults into fault classes and when possible indicates why a fault was not detected.

Reports active feedback bridging fault cases dynamically during simulation.

Accommodates a fault list manager for fault filtering based on hierarchy and substrings of net names and provides store, load and print fault lists.

Provides an efficient mechanism integrated with the SCPAI (Simulator C Programming Application Interface) for fault effect propagation and management of faulty state deviations of sequential user-created C modules in concurrent fault simulation mode. The user has full control of performance by choosing a certain composition of gate-level modules and SCPAI modules depending on design complexity and computational resources available.

Provides a mechanism for initializing all sequential elements to any logic state prior to fault simulation to speed up simulation of functional patterns that contain significant amount of embedded initalization and reset code.

Supports charge storage nodes and keepers in concurrent fault simulation.

Available options and packages

The logic simulator and fault simulator are available with and without the programming application interface ( SCPAI). See packages available for simulator options available for various system platforms.

The fault simulator packages include the corresponding logic simulators with full set of features. Several examples of circuits and simulator settings are included in all packages.