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DFTSimuLab provides affordable
solutions for efficient logic simulation and fault simulation.
The Verilog HDL compatible logic simulator, VDLsim, and fault simulator, VDFsim, combine gate-level models with behavior-level
models to enable
flexible scalability of simulation tasks over design complexity.
The fault simulator supports
a wide range of fault models including standard stuck-at fault models and
several bridging fault models and accepts extended Verilog netlist representations.
The simulators provide a variety of useful verification and testability checkers
including feedback analysis, contention checking and toggle coverage
analysis.
DFTSimuLab also provides customization of simulation/fault modeling tools for
various DFT tasks including fault grading and fault coverage and testability analyses.
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